To determine the parameters of power devices (such as IGBT, MOSFET, SiC/GaN devices, etc.) in solar inverters, it is necessary to focus on the system specifications, topology, operating conditions, and reliability requirements of the inverter. The core is to ensure the safe and efficient operation of power devices under all operating conditions, while balancing cost and performance. The following is a step-by-step parameter determination method, covering key parameter definitions, computational logic, and engineering considerations.
1、 Prerequisite: Clarify the core system parameters of the inverter
The parameters of power devices are directly determined by the "input/output requirements" of the inverter, and the following system level indicators need to be locked first, which is the basis for parameter calculation
2、 Core parameter 1: Rated voltage (V ₍ₐₘₛ₎/V ₘₐₓ) - to avoid breakdown
The rated voltage of power devices should cover the maximum instantaneous voltage stress they can withstand during operation, and should be calculated based on the topology structure. The core principle is that the rated voltage of the device should be greater than or equal to the maximum voltage stress multiplied by the safety margin (usually 1.2-1.5 times).
1. Calculate the "maximum voltage stress" (based on topology)
In different topologies, the voltage stress borne by power devices varies significantly. The following are the voltage stress calculations for common topologies:
Single phase full bridge topology (commonly used for string inverters):
The DC bus voltage (V_bus) is crucial, and the maximum voltage that the device can withstand when turned off is V_bus (due to the complementary upper and lower bridge arms in the entire bridge, the turning off device needs to withstand the bus voltage).
Example: 1500V input, bus voltage 1500V, device voltage stress=750V, margin 1.2 times, select devices with rated voltage ≥ 900V (such as 1200V SiC MOSFET, leave a larger margin).
2. Key points to note
Need to consider voltage fluctuations in the power grid (if the grid voltage allows for ± 10% fluctuations, it should be included in the fluctuation of the bus voltage);
It is necessary to prevent transient overvoltage of switches (such as parasitic inductance overvoltage caused by dv/dt when the device is turned off, which needs to be suppressed by buffer circuits or reserved with 5%~10% margin);
The temperature coefficient of breakdown voltage for SiC/GaN devices is positive (temperature increases, breakdown voltage increases), but for IGBT it is negative (temperature increases, breakdown voltage decreases), and the margin needs to be adjusted accordingly (IGBT margin can be appropriately increased).
3、 Core parameter 2: Rated current (I ₙₒₘ/I ₘₐₓ) - to avoid overcurrent burnout
The rated current of power devices should cover the maximum instantaneous current they can withstand during operation, including rated operating current, overload current, and fault current. The principle is that the rated current of the device should be greater than or equal to the maximum current stress multiplied by the derating factor (based on temperature/heat dissipation).
1. Calculate the "maximum current stress" (under different operating conditions)
Current stress needs to be calculated in two scenarios: "steady-state operation" and "transient/overload":
(1) Steady state rated current (I ₛₜₑₐ dy)
According to the rated power and topology of the inverter, calculate the effective value current or peak current of the computing device under rated operating conditions:
Single phase full bridge:
Output active power P ₙₒₘ=V ₒᵤₜ (AC RMS) × I ₒᵤₜ (AC RMS) × PF (power factor, usually 0.9~1.0);
The device current is the bridge arm current, with an effective value of I2=I ₒᵤₜ× √ 2/2 ≈ 0.707 × I ₒᵤₜ (as the full bridge output current and bridge arm current are the superposition of square waves and sine waves, Fourier analysis or simulation verification is required);
Example: 5kW single-phase inverter, 220V output, PF=1.0, I ₒᵤₜ=5000/220 ≈ 22.7A, device current effective value ≈ 0.707 × 22.7 ≈ 16A, peak current ≈ 22.7 × √ 2 ≈ 32.1A.
Three phase full bridge:
Output power P ₙₒₘ=√ 3 × V ₒᵤₜ (line voltage) × I ₒᵤₜ (line current) × PF;
The device current is the phase current, with an effective value of I2=I ₒᵤₜ (because the three-phase bridge arm current is equal to the output line current), and the peak current ≈ I ₒᵤₜ× √ 2;
Example: 100kW three-phase inverter, 380V line voltage, PF=1.0, I ₒᵤₜ=100000/(√ 3 × 380) ≈ 152A, device current effective value ≈ 152A, peak value ≈ 215A.
(2) Transient/Overload Current (I ₜᵣₐₙₛ)
Consider the overload capacity of the inverter (such as 1.2 times overload lasting for 1 minute), power grid faults (such as current surge when low voltage crosses LVR), and startup surge:
Overload current: I ₒᵥₑᵣ=overload multiple × I ₛₜₑₐ dy (peak value);
LVR current: According to grid standards (such as GB/T 19964), the current at low voltage should reach 1.5~2 times the rated current for 0.1~2 seconds;
Example: The above 100kW inverter requires a peak current of 215A × 2=430A during LVR, and the device must be able to withstand this transient current.
2. Current derating (key engineering step)
The "rated current" in the device manual is usually the maximum value at a shell temperature of 25 ℃ (Tc=25 ℃), but in actual inverter operation, the shell temperature may reach up to 60 ℃~80 ℃, and it needs to be rated according to the junction temperature current curve:
Junction temperature Tj=shell temperature Tc+device power consumption P_loss × thermal resistance Rth (j-c) (junction to shell thermal resistance);
When Tj increases, the maximum current allowed by the device will decrease (for example, when IGBT is at Tj=125 ℃, the rated current may only be 70% of that at 25 ℃);
The derating coefficient is usually taken as 0.7~0.9 (depending on the heat dissipation design capability, the better the heat dissipation, the smaller the derating coefficient).
Example: The device manual states that the rated current is 200A at 25 ℃, and the current drops to 140A (with a derating factor of 0.7) when Tj=125 ℃; If the actual temperature is 100 ℃ and the current obtained from the curve is 160A, combined with the maximum LVR current of 430A, multiple devices need to be connected in parallel (such as three 160A devices connected in parallel, with a total current of 480A ≥ 430A).
4、 Core parameter 3: Switching loss and conduction loss (P ₗₒₛₛ) - determines the heat dissipation design
The losses of power devices directly affect the efficiency of the inverter and the design of the heat dissipation system. It is necessary to calculate the conduction losses (P ₒₙ) and switching losses (P ₛᵥᵢₜₕ) to ensure that the total losses are within the range of heat dissipation capacity (i.e., Tj ≤ the maximum junction temperature of the device, Tj ₘₐₓ, usually 125 ℃ or 150 ℃).
1. Conduction loss (P ₒₙ)
The product of the voltage drop (V_c ₑₛₐₜ, such as V_ce (sat) of IGBT and V_d ₛₒₙ of MOSFET) when the device is conducting and the current should be calculated based on the effective value of the current waveform
IGBT conduction loss: P ₒₙ=V_ce (sat) × I2 ₑᵥ (effective current value) × duty cycle D;
MOSFET conduction loss: P ₒₙ=I2 ₑᵥ ² × R_d ₛₒₙ (conduction resistance) × D;
Note: V_ce (sat) and R_d ₛₒₙ increase with the increase of junction temperature (for example, the V_ce (sat) of IGBT is 20%~30% higher at Tj=125 ℃ than at 25 ℃), and the actual parameters at the junction temperature need to be used for calculation.
2. Switch loss (P ₛᵥᵢₜ c ₕ)
Including turn-on loss (E ₒₙ) and turn off loss (E ₒ ff), proportional to the switching frequency f ₛ:
Main switch loss: P ₛᵥᵢₜ c ₕ=(E ₒₙ+E ₒ ff) × f ₛ × duty cycle D;
E ₒₙ/E ₒ ff needs to be retrieved from the device manual (usually providing loss curves at different voltages, currents, and junction temperatures, such as E ₒₙ=5mJ at V_bus=1000V, Ic=200A, and Tj=125 ℃);
Key influencing factors: The higher the switching frequency, the greater the switching loss (such as when f ₛ increases from 10kHz to 50kHz, the switching loss increases by 5 times). Therefore, high-frequency inverters (such as SiC inverters) should prioritize selecting devices with low switching loss.
3. Matching of losses and heat dissipation
The total loss P_total=P ₒₙ+P ₛᵥᵢₜ c ₕ, which needs to meet:
T_j = T_c + P_total × R_th(j-c) ≤ T_jₘₐₓ
If the calculated value of Tj exceeds the maximum value, adjustments need to be made:
Reduce switch frequency (decrease switch losses);
Choose devices with lower V_ce (sat)/R_d ₛₒₙ (to reduce conduction losses);
Optimize heat dissipation design (reduce Tc or Rth (j-c), such as using larger radiators, fans, liquid cooling).
4、 Other key parameters: reliability and compatibility
In addition to voltage, current, and losses, the following parameters should also be considered to ensure compatibility and long-term reliability between the device and the system
5、 Summary: Parameter determination process (engineering implementation steps)
Clarify system requirements: lock the rated power of the inverter, input/output voltage, switching frequency, topology, and ambient temperature;
Simulation and testing verification: Device stress is verified through PSIM/Saber simulation, actual junction temperature and losses are tested on the prototype, and final iteration parameters are determined.
Through the above steps, it can be ensured that power devices can operate safely, efficiently, and reliably while meeting the performance requirements of the inverter, avoiding device damage or system failures caused by improper parameter selection.
